Ceramic chip capacitor having coplanar surfaces

ABSTRACT

A ceramic chip electrical capacitor, primarily for use in hybrid integrated circuits. The capacitor has a body of one type conductivity ceramic material with a pair of embossed coplanar surfaces and a groove separating the surfaces. A layer of electrically conductive material is upon each of the coplanar surfaces forming electrodes on the respective surfaces. The electrodes include dopant material, productive of the other type conductivity in the ceramic material, diffused into the surfaces to form a PN-junction dielectric region in each of the surfaces beneath the respective electrodes.

O United States Patent 13,566,204

[72] Inventors James P. Callahan [56] References Cited g g'g i m Des PM In UNITED STATES PATENTS 9 "I65, [2]] Am No 5 3,098,160 7/1963 Nayce 317/23sx A 4 3,35 l l Khauri 3 l Division of Ser. No. 625,459, Mar. 23, 1967. 3,419,759 12/1968 l-layakawa 3l7/230 [45] Patented Feb. 23, 1971 3,414,441 12/1968 Girshemzon et al. 3l7/235X [73] Ass'gnee mm' t Primary'Eiaminer-James D. Kallam I Attorneys Richard H. Childress and Robert F. Meyer ABSTRACT: A ceramic chip electrical capacitor, primarily [54] CERAMIC CAPACH-OR HAVING for use in hybrid integrated circuits. The capacitor has a body COpLANAR ES of one type conductivity ceramic material with a pair of em- 20 Claims, 7 Drawing Figs. bossed coplanar surfaces and a groove separating the surfaces. [52] Us m 317/230 A layer of electrically conductive material is upon each of the 317/538 317/101 coplanar surfaces forming electrodes on the respective sur- [51] In. (1 5 faces. The electrodes include dopant material, productive of "01 3/06 the other type conductivity in the ceramic material, diffused [50] Field of 317/230, into the surfaces to form a PN-junction dielectric region in 231, 232, 233, 234, 235 each of the surfaces beneath the respective electrodes.

- SLURRY PREPARATION FILM FORMING FILM DRYING FILM CUTTING FIL M LAMINATION.

WAFER EM BOSSING FIG I BINDER BURNOUT AIR FIRING REDUCTION FIRING PASTE APPLICATION ELECTRODE FIRING PERFORMANCE TESTING INVENTORS JAMES P. CALLAHAN RICHARD A. STARK WAFER D ICING PATENTED FEB23 I97| SHEET 2 OF 3 INVENTORS JAMES P. CALLAHAN RICHARD A. STARK PATENTEUFEBNIBH Y SHEET3UF3 NVENTORS CALL CERAMIC CHIP CAPACITOR HAVING COPLANAR SURFACES This is a division of application Ser. No. 625,459, filed Mar. 23, 1967.

Miniature chip capacitors and other chip components are useful primarily in connection with hybrid integrated circuits and microminiaturized printed circuits. Ceramic chip capacitors provide higher capacitance values than those attainable in monolithic integrated circuits. In order to meet its intended uses, a chip capacitor should enclose a high electrical capacitance within a small volume; it should also be capable of simple and inexpensive manufacture. Additionally, hand positioning and assembly of the capacitors into a circuit should be eliminated to the greatest possible extent. Furthermore, since such components are essentially custom-made in batches to a circuit manufactures capacitance, voltage, size and shape requirements, tooling and setup costs should be low.

It is accordingly an object of the present invention to provide miniature chip components having inherently coplanar electrodes for direct assembly into printed or integrated circuits, and to provide such components having a form and structure easily adaptable for use with common automated handling and assembly equipment.

Other objects and advantages, as well as modifications obvious to one skilled in the arts to which the invention pertains, will become apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a process according to the invention;

FIG. 2 illustrates, in simplified forms and partial schematic, elements of an apparatus according to the invention, some of the elements being drawn to different scales;

FIG. 3 is a cross-sectional view of an embossing die and a ceramic wafer of the invention;

FIG. 4 is a perspective view of a completed ceramic wafer according to the invention;

FIG. 5 shows an individual chip capacitor unit diced from the wafer of FIG. 4;

FIG. 6 is a cross-sectional view of a capacitor unit taken along the line 6-6 of FIG. 5; and

FIG. 7 shows the capacitor unit of FIG. 5 mounted in a circuit.

Referring more particularly to the drawings, a ceramic material is first prepared as a fine-textured slurry from the raw ingredients by a means generally indicated by the numeral 10, here shown to be a blade-type mixer having a container 11 provided with a shaft 12 carrying a number of rotating blades 13 and driven by a motor 14. This type of mixer is used in preference to a ball mill or other means to insure faster and more even dispersion of the ingredients and to avoid breaking down the emulsion from excessive mechanical action. The constituents of the slurry include a ceramic filler, a plastic or flowable temporary binder and other, conventional material such as release agents and antifoaming agents. If the ceramic will subsequently be reduced as described hereinafter, it must be a form of oxide ceramic. Thermoplastic binders such a polyvinyl alcohol, polyvinyl chloride, nitrocellulose and acrylic are desirable in that they are volatile and leave a low ash content in the mature ceramic. The percentage of binder required is somewhat higher than normal usage in other applications; binder content typically ranges from 12 to 15 percent. For the sake of continuity, the example of a chip capacitor using a barium titanate oxide ceramic and a thermoplastic binder will be followed throughout the description. In general, the alkaline earth titanate and zirconate families of ceramic and titanium dioxide have been found suitable for the present purposes.

The slurry is next formed into a film by casting, extrusion, spraying or other means. The casting technique yields good results with a minimum of cost and complexity. FIG. 2 illustrates a continuous film-casting machine 15, in which the slurry is fed from a hopper 16 onto a driven stainless steel belt 17.

The belt '17 is coated with a separate release agent such as silicone oil or ammonium stearate by a wick 18 to prevent the film'from sticking thereto. Alternatively, the belt 17 may be coated with a permanent release agent such as Teflon. As the slurry moves along the belt, it is formed into a continuous film 19 by passing under a doctor blade 20 whose height above the belt 17 is precisely controlled by the micrometer screws 21. The wet film is dried in an oven 22; drying a 6-mil thick film typically requires approximately 5 minutes at 250 F. The green film 19 then emerges from the oven 22 and is removed from the belt 17 by a parting blade23. At this point the film 19 has sufficient mechanical strength and flexibility to withstand tensile stress and handling without damage.

A filmcutting unit, indicated generally by 24, accepts the green film 19 from the casting machine 15. The film is first sheared into strips 25 by a series 9f knives 26 and then into pieces or squares 27 by a cutoff knife. The rollers 29 support the strips 25 and pull them through the cutting unit 24. The squares 27 slide down a chute 30 into a bin 31. Maximum size of the squares 27 is limited primarily by the extent to which warping during air firing can be tolerated in subsequent steps, as will be more fully described hereinafter. Presently used squares may typically range from I to 4 inches on a side.

Capacitors made by the present technique are commonly about 15 mils thick, but the film-casting process is most economical and efficient at a film thickness of 4 to 7 mils. Therefore, the sheared squares 27 are stacked to fon'n a laminated wafer 32 of the desired thickness. Lamination also provides a greater mechanical strength and eliminates any pinhole defects which may occur because of trapped air in the individual squares 27. The squares 27 may conveniently be stacked by hand as the resulting wafer 32 is placed in the embossing unit 33. The wafer 32 is coated with a release agent and heat and pressure are applied thereto by means of heating elements 34 and a hydraulic cylinder 35 acting through a die 36 and a pressure block 37. The parameters will vary with the type of binder used and with other factors; typical range are 75-400 F. and WOO-20,000 p.s.i. The embossing operation impresses the pattern of the die into the wafer 32', it also bonds the individual squares 27 inextricably together and acts to remove any remaining air bubbles from the wafer. Although more sophisticated embossing means could be used, such as the continuous rolling dies found in the plastics industry, it is felt that the relatively small amounts of material required for even a very large number of individual components and the small size of the wafers will rarely justify the expense of the more complicated machinery, dies and handling equipment.

FIG. 3 shows an enlarged cross-sectional view of the embossing die 36 and the embossed and bonded wafer 32'. The boundaries of the individual capacitor units 38 are defined by a set of reticulate grooves 39 formed by corresponding ridges 40 in the die 36. The grooves 39 are V-shaped in order to provide cleavage lines for dicing the wafer at a later stage; they also inhibit warping of the wafer during firing to some extent. A series of substantially U-shaped grooves 41 is formed in the wafer by corresponding ridges or ribs 42 in the die. The draft angles of the ribs 42 are only sufficiently great to allow proper release of the wafer from the die. The shape and shallowness of the grooves 41 insures that the capacitor units 38 will not be broken in half when the wafer 32 is diced. The coplanar surfaces 43 are maintained in a flat condition by the action of the depressed surfaces 44 of the die. The depression 45 provides a flange 46 around the edges of the wafer 32' to avoid imperfections in the outermost capacitors of the wafer. A wall 47 may surround the depression 45 to trim the edges of the wafer 32' and to insure proper formation of the pattern thereon by preventing leakage of the wafer material from the sides of the die 36. The wafer material becomes hot enough to flow to some extent during the embossing operation, and the wall 47 gives a coining effect to this operation. It will be noted that the die 36 presses and flowslhe wafer material rather than cutting it, so that the material is pushed laterally away from the grooves 39 and downward in the areas underlying the grooves 41. Therefore, the material under the latter grooves is compacted and strengthened, while that under the grooves 39 is not so strengthened; this effect further assures that cleavage will occur alongthe proper lines. In a typical wafer of l5-mil thickness, the grooves 39 will be approximately mils deep and the grooves 41 approximately 5 mils deep.

The die 36 must be made of a hard material to withstand a large number of embossing operations without undue wear. Hardened beryllium copper is asuitable die material in this regard; for short'production runs,,an inexpensive epoxy die is feasible. In practice, the die is made easily and inexpensively by casting thernolten die material into a mould .(not shown) having a face containingthe grooved .pattern of the wafer 32'. Since the grooves 39 and4l usually extend continuously across the surface of the entire wafer, the corresponding grooves may beeasily machined into the mould by asimple milling operation. The die is cast'into the mouldand then hardened by conventional methods. The die 36 may also be made byaninvestment'casting process. It will be noted that the die 36 is the only specialized tooling required for a particu-. lar production run, so that short'runs of components built to custom specifications of'size and shape are eminently practical The embosse'dwafer 32, still in a relatively strong and flexible condition, is next transferred to a furnace 48' for-binder burnout. The plastic binder is here volatilized' and driven o ut of the ceramic, its function of providing strength and flow characteristics to thegreen ceramic having been performed. Temperature cycles for burnout depend upon the particular binder material employed andgwith its weight percentage. For a 12 percent polyvinylchloride binder, furnace temperature may conveniently be changed in 1-hour steps in the cycle 400- 6 00800900--1000 F. It will'be appreciated that other methods of removing the temporary, binder from the greenceramic are equally satisfactory. The ceramic material itself is not affected by this step, except for a mechanical weakening occasioned by loss of the'binder.

After its removal from the furnace 48, the wafer 32' is placed on a driven belt 49 for air firingin a first kiln 50 of an apparatus 51. There the wafer 32. is matured by the application of heat in an air atmosphere, maintained by the flue 52. For abarium titanate ceramic, this conventional air firing step requires approximatelyhours at a temperature of 2400" F. plus cool-down time. Although air firing 'couldbe accomplished in the furnace 48 after theb'urnout step, contamination of this furnace by the binder products remaining therein makes it desirable to firein a separate furnace or kiln. Air fir-' ing shrinks the wafer approximately 20 percent in its linear dimensions; it'also tends to warp the wafer somewhat, as was mentioned "previously. "The mature oxide ceramic must be made semiconducting for many of the applications envisaged by the invention; therefore, asecond kiln 53 of the-apparatus 51 is provided with areducing atmosphere by a hydrogendelivery pipe Stillusing the example of a barium titanate capacitor, the removaliofoxygcn by the, hydrogen yields an excess of titanium in the ceramic, which has the effect of making the ceramic an N-type polycrystalline semiconductor, The reduction process is continued until' a sufficiently low and homogenous bulk resistivity: is attained. Barium .titanate wafers 15 mils thick typically require one hour at 2500F. for proper reduction.

The matured and reduced wafer 32' exits the compartment 53 on the belt 49 and is transferred for'electrode application to a printing means 55, here shown as a conventional and inexpensive hand printing press. A number of wafers 32'is heldon the platen 56 by a vacuum holder 57'supplied by a vacuum line 58. An electrode paste '59 is placed on the rotatable inking plate 60; and inking roller 61. picks up the paste from the inking'plate and applies it to the raised coplanar surfaces 43 of thewafer 32'by movement of the handle 62 and yoke 63. The

' paste 59 containsanelectrode material of a noble metal, such as palladium, platinum or gold, or silver in flake or particle form and a bonding agent of-a glassy nature, such as glass particles', it also contains a low-temperature adhesive and a vehicle .to give the paste the proper consistency to cause it to adhere to the surfaces 43 in the samemanner inwhich ink is applied to an engraved plate in the printing of-papers; that is. the consistency of the paste is suchthat it remains on the surfaces 43 and does not run into the grooves 39.land.4 l. it is by this :rovel'technique of embossing and printingthat all conventional requirements for expensive photographic orsilk-screen masks and precision mask alignment are eliminated. In effect, the embossed wafer 32'is made to serve as its own template, and the electrode paste 59, is thus automatically applied to the correct areas. A limiting factor in this printing process arises from an increased warping of the wafers 32'as their size is increased, which ultimately results in an uneven distribution of paste onto the surfaces 43. This problem, however, may be alleviated byseveralmethods. The effect of the grooves 39. has been mentioned previously in this connection. Other solutions include the special selection of ceramic materials to reduce warping during airfiring and modification of the standard rubber printing roller 61 to allow itto follow the gentle curves of the warped surfaces but not the'sharp angles of the grooves 39and4l.

An electrode firing step follows the electrode paste application. This operation typically requires approximately 15 minutes at a temperature of 'l40()l500F. in a furnace 64. Electrode firing is normally done .in-air, although a different atmosphere may be desirable in some cases, as well be pointed out hereinafter. A basic purpose of electrode firing is to diffuse the materials of the electrode paste into the surfaces of the ceramic wafer material. Diffusion of the metal and glassy materials into the ceramic of course bonds the electrode layer 65 thereto, and the low-temperature adhesive may therefore be driven out during firingQBut the diffused constituents of the paste also act as a P-typedopant, so that PN junctions 66 are created in the alloyed regions 67. Since the semiconducting ceramic has a low bulk resistivity, the junctions become the dielectric of the completed individual capacitor units 68. The two junctions 66 of an individual unit are placed back-toback, so that one of them is always reverse-biased and the capacitor 68-is therefore nonpolarized. The U-shaped medial groove 39 prevents the capacitor from being short-circuited by contact directly between the two alloyed regions 67.

lf'the electrode firing takes place in the presence of oxygen, parts of the reduced ceramic will be thermally reoxidized to some extent. Morespecifically, reoxidation occurs in the alloyed regions 67, imparting an error-function gradation to the PN junctions '66. In effect, the reoxidation forms another dielectric, which decreases the capacitance of the unit 68. The decrease in capacitance, howeven is accompanied by an inereaseinvoltage rating, a lower leakage current, and less voltage-dependence of the capacitance. Reoxidation also increases the mechanical strength of the bond between theelectrode layers 65 and the ceramic. The use of an atmosphere 7 other than air in the electrode firing step will of course influence the rate at which thermal reoxidation proceeds; in addition, the use of a low firing temperature over a long time interval promotes the alloying or diffusion process, while a high temperature applied over a short interval enhances reoxidation. That is, the rates of'diffusion and'reoxidation may be differentially controlled to obtain certain desired characteristics in the capacitor. I

Capacitance tolerance and other electrical tests of the individual units 68 are performed on a wafer test unit 705The completed wafer 69, the wafer'32' beinga substrate or body thereof, is'p'laced on a jig '71 which is coupled to a low-speed servodrive 72. As the units 68 pass under the test head 73, they arecontacted by a row of adjustable probes 74 and the appropriate measurements are taken. Since the electrodes 65 ble portion ofthe cost of mass-produced microminiature components "results from the necessity for manual testing procedures. The present invention reduces this burden by providing an inherent means for'automatic testing. Because the capacitors 68 are checked insiteon the wafer 69, a

method of identifying defective units is required. Tothis end,

the probe 74 may, for instance, be fed with a magnetic ink to be released by the test unit onto defective units for culling by a magneiic' sensor ('n'ot-shownlprior to packaging. i v

A further advantage of the present invention appears in the wafer dicing, whereby .the individual capacitors 68 are separated from each other for packaging and shipment. Placing the wafer 69 on a soft rubber pad 75 and passing a hard roller 76 of small diameter thereover in the directions of the arrows 77 will break the wafer cleanly along the reticulate grooves 39. A piece of adhesive tape 78 under the wafer 69 prevents the small pieces from scattering as they are broken. As has been mentioned, the absence of compaction in the vicinity of these grooves and their sharp. V-shape promote cleavage therealong. The resulting edges 79 appear smooth and perpendicular to the base surface 80 of the capacitor 68 even under a microscope. Conversely, no evidence of fracture has been observedin the U-shaped medial grooves 41. The simplicity of this dicing step may render it feasible in some cases to ship the wafer intact for dicing by the buyer, in order to reduce counting and packaging costs.

FIG. 7 shows a completed chip capacitor 68 positioned on the substrate 81 of a portion of hybrid integrated circuit or a miniature printed circuit. The capacitor 68 is placed face downward on the substrate 81 so that the electrodes 65 meet the contact pads 82 of the circuit; these elements are then soldered or joined by other conventional means. To avoid the handling of a multitudeof small pieces, automatic means are commonly used in the industry to" feed, position and orient such components. Rotational orientation about an axis perpendicular to the plane of the component may conveniently be accomplished with guides operating from a vibratory feeder. It will be noted from FIG. 7 that a quadrantal ambiguity in rotation of a square component in the direction of the arrow 83 may be rendered harmless by diagonal mounting on the pads 82. A much more severe problem occurs in attempting to distinguish between the upper and lower surfaces for orientation purposes. Because conventional chip components are featureless except for thin contact stripes deposited on one face, the vacuum holder usually employed for positioning cannot differentiate between these two-surfaces without some form of sensing equipment. The present unit 68, however, has a substantially deep groove 41 running the length of the surface to be placed downward on the substrate 81. Therefore, a vacuum holder cannot pick up the unit 68 except by the face 80 because of air leakage through the groove 41. Units thus rejected for improper presentation then return to the vibratory feeder for another pass. Accordingly, a major advantage of components fabricated in the present manner resides in the fact that the means most commonly used for automatic parts placement may be made to serve without auxiliary equipment as an orientation discriminator. it is also possible, of course, to provide a ridge on a handling machine or feeder, the ridge being keyed to the groove 41 for proper orientation of the component 68; furthermore, the difference in light reflective characteristics between the layers 65 and the surface 80 will, allow the use of a photoelectric means as an orientation discriminator.

Chip capacitors according to the invention may vary greatly in size. A capacitor 60 mils square typically has a capacitance range of approximately 50 picofarads at a design rating of 50 volts to 15,000 picofarads at 3 volts. Electrical parameters of the unit may be adjusted in a number of ways. Changing the outer dimensions or the width of the grooves 41 will of course influence the capacitance; it has been remarked that such dimensional changes involve merely the substitution of a different embossing die. Variation of capacitance and voltage rating by tailoring the respective diffusion and reoxidation I rates during electrode firinghas been mentioned. his also possible to adjust'the capacitance by proper selection of electrode materials, since different materials have different diffusion rates on a given electrode surface.

It has been found that capacitors fabricated according to the invention has have a nonlinear, voltage-dependent leakage resistance, decreasing from extremely high at low voltages to a lower value at the dielectric breakdown voltage. Consequently these capacitors are voltage-rated at a point above which the leakage current begins to increase to an objectionable extent. Since catastrophic breakdown of the dielectric does not occur until a much higher voltage is reached, irreversible failure of the capacitor is avoided even at large voltage overloads. It may also be desirable to employ the capacitor'intentionally as a high-value nonlinear resistor and thereby take direct advantage of this characteristic as a circuit design feature.

It will also be appreciated that the advantages of the present capacitor unit resulting from its novel structure are not dependent upon the particular method of its fabrication. Therefore, having described the foregoing preferred embodiments by way of illustration rather than by way of limitation, we claim as our invention:

We claim: 7

' l. A ceramic'chip electrical capacitor, comprising a body of one'type conductivity semiconductive ceramic material having a pair of embossed coplanar surfaces and a groove in said body separating said surfaces,'a layer of electrically conductive material upon each of said coplanar surfaces forming electrodes on the surfaces respectively, said electrodes including dopant material, productive of the other type conductivity in said ceramic material, diffused into said surfaces and forming PN-junction dielectric region in each of said surfaces beneath the electrodes respectively.

2. The capacitor of claim 1 wherein said ceramic material is an oxide ceramic.

3. The capacitor of claim 2 wherein said oxide ceramic is selected from the class consisting of alkaline earth titanates, zirconates and titanium dioxide.

4. The capacitor of claim 1 wherein said electrode material contains a bonding agent. 7

5. The capacitor of claim 1 wherein said electrode material contains a metal selected from the class consisting of silver, palladium, platinum and gold.

6. A ceramic chip electrical capacitor, comprising a body of chemically reduced, semiconducting oxide ceramic filler having a plurality of embossed, coplanar surfaces and a substantially U-shaped groove, and a semiconductor-dopant material diffused into said coplanar surfaces forms a PN junction in said body beneath each of said coplanar surfaces.

7. The capacitor of claim 6 wherein portions of the ceramic material of said body are partially reoxidized.

8. The capacitor of claim 7 wherein said PN junctions are graded as a result of said reoxidation.

9. A ceramic chip electrical component, comprising a body of ceramic material, said body having a plurality of coplanar surfaces and at least one groove separating said surfaces, and an electrode layer bonded to said coplanar surfaces.

10. The component of claim 9 wherein said ceramic has semiconducting properties, and wherein said electrode layer is diffused into said coplanar surfaces.

11. The component of claim 10 further comprising a plurality of rectifying junctions located in said semiconducting ceramic body beneath said coplanar surfaces.

12. A component according to claim 11 having a nonlinear electrically resistive characteristic.

13. The component of claim 9 wherein at least one of said grooves is substantially U-shaped.

14. The component of claim 9 wherein said body has an essentially flat and featureless surface opposite said coplanar surfaces.

15. A component according to claim 9 having a controlled electrically resistive characteristic.

19. A ceramic wafer having a plurality of electrical components, said wafer comprising a reduced, semiconducting ceramic substrate having a plurality of coplanar surfaces and a groove separating said surfaces, a layer of electrically conductive material diffused into said coplanar surfaces, and a plurality of PN junctions each of which underlies one of said coplanar surfaces.

20. The wafer of claim 19 wherein portions of said ceramic substrate are partially reoxidized. 

1. A ceramic chip electrical capacitor, comprising a body of one type conductivity semiconductive ceramic material having a pair of embossed coplanar surfaces and a groove in said body separating said surfaces, a layer of electrically conductive material upon each of said coplanar surfaces forming electrodes on the surfaces respectively, said electrodes including dopant material, productive of the other type conductivity in said ceramic material, diffused into said surfaces and forming PNjunction dielectric region in each of said surfaces beneath the electrodes respectively.
 2. The capacitor of claim 1 wherein said ceramic material is an oxide ceramic.
 3. The capacitor of claim 2 wherein said oxide ceramic is selected from the class consisting of alkaline earth titanates, zirconates and titanium dioxide.
 4. The capacitor of claim 1 wherein said electrode material contains a bonding agent.
 5. The capacitor of claim 1 wherein said electrode material contains a metal selected from the class consisting of silver, palladium, platinum and gold.
 6. A ceramic chip electrical capacitor, comprising a body of chemically reduced, semiconducting oxide ceramic filler having a plurality of embossed, coplanar surfaces and a substantially U-shaped groove, and a semiconductor-dopant material diffused into said coplanar surfaces forms a PN junction in said body beneath each of said coplanar surfaces.
 7. The capacitor of claim 6 wherein portions of the ceramic material of said body are partially reoxidized.
 8. The capacitor of claim 7 wherein said PN junctions are graded as a result of said reoxidation.
 9. A ceramic chip electrical component, comprising a body of ceramic material, said body having a plurality of coplanar surfaces and at least one groove separating said surfaces, and an electrode layer bonded to said coplanar surfaces.
 10. The component of claim 9 wherein said ceramic has semiconducting properties, and wherein said electrode layer is diffused into said coplanar surfaces.
 11. The component of claim 10 further comprising a plurality of rectifying junctions located in said semiconducting ceramic body beneath said coplanar surfaces.
 12. A component according to claim 11 having a nonlinear electrically resistive characteristic.
 13. The component of claim 9 wherein at least one of said grooves is substantially U-shaped.
 14. The component of claim 9 wherein said body has an essentially flat and featureless surface opposite said coplanar surfaces.
 15. A component according to claim 9 having a controlled electrically resistive characteristic.
 16. A ceramic wafer having therein a plurality of electrical components, said wafer comprising an embossed ceramic substrate having a plurality of coplanar surfaces and a plurality of reticulate grooves separating said surfaces and defining said components, and an electrode layer of an electrically conductive material bonded to said coplanar surfaces.
 17. The wafer of claim 16 wherein the grooves of a reticulate set of said reticulate grooves are substantially V-shaped.
 18. The wafer of claim 16 wherein the grooves of a spaced series of said reticulate grooves are substantially U-shaped.
 19. A ceramic wafer having a plurality of electrical components, said wafer comprising a reduced, semiconducting ceramic substrate having a plurality of coplanar surfaces and a groove separating said surfaces, a layer of electrically conductive material diffused into said coplanar surfaces, and a plurality of PN junctions each of which underlies one of said coplanar surfaces.
 20. The wafer of claim 19 wherein portions of said ceramic substrate are partialLy reoxidized. 